1. Technical Field of the Invention
This invention relates to an apparatus and method for testing the cycle time of functional circuits. More specifically, it relates to an on-chip programmable timing circuit for determining the relative performance of functional circuits and to verify chip circuit performance.
2. Background Art
Circuit speeds, i.e., the speed at which logic devices can switch combined with signal transmission rate from device to device, are not identical in all parts of the wafer (or from wafer to wafer) because of uncontrollable inconsistencies in the manufacturing process.
A common method for determining the performance of circuitry on an ASIC chip, after fabrication of the wafer, is through the use of Performance Scan-Ring Oscillators (PSROs). A PSRO circuit is essentially a free-running ring of memory elements passing a pulse (a la a bucket-brigade) the output of which can be measured at a reserved chip output pin. Free-running in this case implies a circuit that is not clocked externally, and will run as fast as the signals can propagate through the logic, i.e., limited only by the capabilities of the technology and manufacturing process variations. The periodicity of the PSRO output provides a relative indication of circuit speed, i.e., shorter period means faster circuit speed. PSROs are used to gauge the quality of the fabrication process, determine the speed of the circuitry on various parts of the wafer, and thereby grade the performance of individual chips on the wafer, before and after dicing. There is usually more than one PSRO on a large ASIC so that process variation within the chip can be taken into account.
PSRO timings are used by manufacturing to sort chips so they can be packaged under separate part numbers according to circuit speed. After the chips are packaged (mounted on module substrates), PSROs may no longer be accessible for re-verification, depending on the design. Development engineering for the ASIC must determine, through a combination of mathematical models and actual testing of the hardware under stress conditions, the relationship between PSRO value and the maximum clock rate at which the ASIC can reliably run, a process called Hardware-Based Cycle-Time (HBCT) analysis. This relationship is combined with other factors to establish the PSRO value(s) used for sorting the chips, i.e., sort point(s).
It is becoming common practice to include HBCT analysis in the determination of sort points since sole reliance on mathematical models based on technology parameters tends towards the conservative resulting in somewhat lower chip yields. Sort points must be established prior to the initiation of mass production, making the timeliness of HBCT analysis critical. With current HBCT methodology, the accumulation and analysis of data is difficult and time consuming.
A circuit path is a combination of logic gates and other devices with interconnecting conductors (transmission lines), as in a logic tree, such that activation or deactivation of an input (at the tip of a branch) can propagate through the tree, when other branches are properly conditioned, to control the output (at the base of the tree). A path usually begins at the output of one latch (or SRAM, GRA, or chip input receiver) and ends at the input of another latch (or SRAM, GRA, or chip output driver).
Path length refers to the time it takes for a polarity change at the input of a path to effect a polarity change at the output. A long path may also be referred to as a slow path.
Cycle time refers to the timing of the clock pulses that pace the operation of the ASIC. It is the elapsed time from the leading edge of one clock pulse to the leading edge of the next pulse of the same clock signal. It might also be stated as a frequency in which case the time from pulse to pulse is implied and can be calculated. Generally speaking, the cycle time must be somewhat longer than the length of the longest path in a design.
Current practice involves finding the longest, i.e., slowest, functional circuits (paths) in the design which are the determinants of the fastest cycle time at which a chip will run. The longest paths are then exercised while increasing the clock frequency, under controlled and/or measured temperature and voltage conditions, until a failure is produced. The major objective is to draw a correlation between fastest cycle time that the chip will run without failing and its measured PSRO time.
During the design of the chip, software based timing tools (mathematical models) are used to calculate the lengths of each path in the design using technology-based parameters. The chip design is greatly influenced by path length calculations since one of the objectives of the design is to produce chips that will operate at (or better than) specific clock frequencies needed to attain compute-performance requirements. It often happens that paths identified as longest by the software timing tools are not necessarily the longest in the actual hardware, if for no other reason than because of "disturb" effects of other circuits which are not factored into the timing calculations.
Long paths that are identified using software timing tools are often very difficult to activate in the actual hardware to allow measurement of the actual path length, particularly if it is not the longest path of the design. In one type of approach, the logic designer must write a unique "targeted" test case that precisely sets up the conditions to cause the object path to be activated. Another requirement of the test case is that failure of the object path must be readily detectable as the clock cycle is gradually shortened.
When the actual hardware is available, it is normally easier and more effective to identify the longest paths through "brute force" testing, although there are drawbacks to this method. For example, a vast array of functional tests, that have been developed to verify the logical integrity of the design, are executed on the hardware at accelerated cycle times during which voltage levels and temperature are recorded. Failures that occur must be analyzed to determine the specific circuit path failing, and whether this path is failing because of its length or other contributing factors. Usually the logic designer will be able to identify the failing path without much difficulty, if the software timing tool has also identified it as a long path. On the other hand, it may require weeks of analysis, depending on the nature of the failure, and then it may only be an educated guess.
The results are typically analyzed in chart form showing the relationship between PSRO value and fastest passing cycle times. The data points must be categorized by type of test performed, and normalized to correct for voltage and temperature deviations.
It is also a goal of HBCT activities to determine how chip fabrication process variations might affect the performance of certain types of circuits as compared to others, e.g., SRAMs, dense/complex logic, long wiring paths, and so forth. With current HBCT techniques it is very difficult to single out a path having the specific characteristics needed for this type of analysis, and be able to make measurements under dynamic conditions.
As previously mentioned, PSRO timings are used by manufacturing to sort chips so they can be packaged under separate part numbers according to circuit speed. Typically, PSRO values are measured and recorded under controlled voltage and temperature conditions before the wafer is diced. Once the chips are mounted on module substrates (chip carriers), these particular PSROs outputs may no longer be accessible for subsequent measurements, i.e., no connection is made between chip I/O pad and a module pin so as to minimize the number of module pins, module size, and thereby cost. This is well and good in the world where mistakes never happen, but experience has been the motivation for some ASIC designs to include additional PSRO circuits and have their outputs connected to module pins so that PSRO values may be re-checked. This capability is of great value during HBCT activities, and also in situations where an error is thought to be caused by a marginal timing condition, perhaps due to a part number mix-up between fast and slow chips, and a simple measurement of the PSROs could bolster the conclusion.
It is an object of the invention to provide an on-chip test circuit for facilitating HBCT activities.
It is a further object of the invention to provide for improved HBCT analysis in the determination of sort points.
It is a further object of the invention to provide an improved capability for testing functional circuits on integrated circuit chips following dicing and mounting of the chips to substrates.
It is a further object of the invention to provide a functional circuit testing capability not requiring test equipment external to the chip containing said circuit.
It is a further object of the invention to provide for programmable configuration of delay on data tapped directly from a functional circuit on an integrated circuit chip.
It is a further object of the invention to provide for circuit timing measurements under dynamic conditions which allow measurement of the actual path length, particularly if the circuit being measured is not the longest path of the chip design.
It is a further object of the invention to provide for circuit timing measurements on functional logic paths having desired characteristics for evaluating chip fabrication process variations which might affect circuit performance
It is a further object of the invention to provide a functional circuit timing measurement circuit which taps directly off of a selected functional path, without adding logic to a possible critical path.
It is a further object of the invention to provide for ready detection of failure of an object path as its clock cycle is gradually shortened.
It is a further object of the invention to provide a capability to test any functional logic path, not just logic associated with buffers.